1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a capacitor of a semiconductor device and a method for manufacturing the same.
2. Discussion of the Related Art
Generally as the capacity of a semiconductor memory device increases, the cell size of the semiconductor memory device decreases. Similarly, in DRAMs (Dynamic Random Access Memories) a decrease in the cell size causes a decrease in the capacitor size. To compensate the decrease in the capacitor size, the thickness of a dielectric layer is gradually decreased. As the thickness of the dielectric layer decreases, however, more leakage current is generated due to tunneling. This reduces reproducibility and reliability of the semiconductor memory device.
In order to prevent such problems, a method of forming a surface with complicated roughness is utilized to increase the effective area of the capacitor. In this method, however, it is difficult to perform a photolithography process because a significant step coverage is formed on the surface, which increases the process cost. Therefore, this method has been found to be unsuitable for highly integrated devices.
Research and development has been directed to innovatively improving the capacity of a capacitor of a semiconductor device and to reducing the surface roughness. One of the methods proposed in this endeavor utilizes materials of high dielectric constant for forming a dielectric film of the capacitor. This provides various positive effects, except that a dielectric constant of such capacitor is not sufficiently high. As a result, such dielectric films do not provide a wide range of applicability, especially in highly integrated systems.
Recently, much attention has been given to ferroelectric substances having a crystal structure known as Perovskite type. Such a ferroelectric substance has become a research object possibly as a dielectric material usable for semiconductor devices.
A ferroelectric substance, in which spontaneous polarization under the Curie temperature appears, generates spontaneous polarization without the electric field. However, these ferroelectric substances easily react to silicon or silicide of a substrate. Further, their surfaces are exposed to strong oxidative circumstances so that they are likely to be oxidized during a thin film formation. PZT (Pb(Zr,Ti)O.sub.3), PLZT ((Pb,La)(Zr,Ti)O.sub.3), BST ((Ba,Sr)TiO.sub.3), BaTiO.sub.3, SrTiO.sub.3, etc. are all examples of a ferroelectric substance.
In order to solve these problems, research and development has been continuously directed to discovering materials and structures which are suitable for electrodes.
FIG. 1 shows a cross-sectional view of the structure of a conventional capacitor of a semiconductor device.
As shown in FIG. 1, an oxide layer 12 is formed on a silicon substrate 11. A predetermined portion of the substrate 11 is exposed to form a contact hole thereon through the oxide layer 12. A silicon plug 13 is formed filing the contact hole up to the top surface of the oxide layer 12. As a lower electrode of the conventional capacitor, a platinum (Pt) layer 14 is formed on the silicon plug 13 and the portions of the oxide layer 12 adjoining the silicon plug 13. Insulating sidewalls 15 are formed on the sides of the Pt layer 14 to provide step coverage for a dielectric layer 16. The dielectric layer 16 and an upper electrode 17 of the capacitor are successively formed on the entire surface inclusive of the Pt layer 14, thereby completing the conventional capacitor of a semiconductor device.
FIG. 2 is a cross-sectional view showing another structure of a conventional capacitor of a semiconductor device.
As shown in FIG. 2, an oxide layer 22 is formed on a silicon substrate 21 and a predetermined portion of the silicon substrate 21 is exposed to form a contact hole thereon through the oxide layer 22. A silicon plug 23 is formed filing the contact hole up to the top surface of the oxide layer 22. As a lower electrode, a ruthenium (Ru) layer 24 is formed on the silicon plug 23 and the portions of the oxide layer 22 adjoining the silicon plug 23. Subsequently, a ruthenium (RU) oxide 25 is formed on the RU layer 24. The lower electrode of the capacitor includes the RU layer 24 and the RU oxide 25. A dielectric layer 26 and an upper electrode 27 are formed on the entire surface inclusive of the lower electrode, thereby completing the conventional capacitor of a semiconductor device.
The above and other conventional capacitors of a semiconductor device have, however, the following problems.
First, as shown in FIG. 3 when forming a platinum layer pattern (Pt) on the plug 13 as a lower electrode using a mask and a dry etch process, a remnant A remains on the sides of the platinum layer so that an accurate Pt pattern cannot be obtained. On the other hand, if a wet etch process is used, under-cuts B as shown in FIG. 4 are formed and an accurate Pt pattern is difficult to achieve.
Second, in the conventional capacitor having a ruthenium layer as the electrode, a significant leakage current is generated because ruthenium has a smaller work function than platinum.